The present disclosures relate generally to semiconductor devices, and more particularly, to a transistor structure and method of making a transistor structure with dual trench for optimized stress effect on a <100> SOI substrate.
In prior techniques, various forms of trench isolation and nitride deposition are known. However, such known techniques do not address providing differential stress on different types of devices and for different orientations, simultaneously.
FIG. 1 is a top view of a CMOS transistor 10 illustrating a channel direction and width direction as is known in the art. In particular CMOS transistor 10 includes an active region 12 and a gate electrode 14, with an underlying gate dielectric (not shown). Active region 12 is characterized by a width dimension W extending in a width direction, the width direction being indicated by reference numeral 16. In addition, active region 12 comprises any suitable semiconductor material. Gate electrode 14 is characterized by a length dimension L extending in a channel direction, the channel direction being indicated by reference numeral 18.
Accordingly, it would be desirable to provide an improved transistor structure and method of making the same for overcoming the problems in the art.